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| AIS326DQ MEMS inertial sensor 3-axis, low g accelerometer with digital output Data Brief Features 3.3 V single supply operation 1.8 V compatible IOs SPI digital output interface(a) 12 bit resolution Interrupt activated by motion Programmable interrupt threshold Embedded self-test High shock survivability ECOPACK(R) compliant (see Section 9) Extended temperature range -40 C to +105 C The AIS326DQ has a user selectable full scale of 2 g, 6 g and it is capable of measuring acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected accordingly to the application requirements. The self-test capability allows the user to check the functioning of the system. The device is available in plastic quad flat package no lead surface mount (QFPN) and it is specified over a temperature range extending from -40 C to +105 C. The AIS326DQ may be used in non-safety automotive applications, such as: QFPN-28 Description The AIS326DQ is a three axes digital output accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. Table 1. Device summary Operating temperature range [ C] -40 to +105 -40 to +105 Anti-theft systems and inertial navigation Motion activated functions Vibration monitoring and compensation Tilt measurements Black boxes, event recorders Order code AIS326DQ AIS326DQTR Package QFPN-28 QFPN-28 Packing Tray Tape and reel a. I2C interface is also available. August 2008 Rev 1 1/49 www.st.com 49 For further information contact your local STMicroelectronics sales office. Contents AIS326DQ Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 QFPN-28 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 2.5 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 2.5.2 2.5.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 3.2 3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 5.1.2 5.1.3 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 7.2 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/49 AIS326DQ Contents 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_Z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 GAIN_X (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Y (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Z (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3/49 Contents AIS326DQ 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Mechanical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Mechanical characteristics at -40 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Mechanical characteristics at 105 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Mechanical characteristics derived from measurement in the -40 C to +105 C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electro-mechanical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . 42 Electrical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Electrical characteristics at -40 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Electrical characteristics at 105 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 9.2 9.3 9.4 General guidelines about soldering surface mount accelerometer . . . . . 44 PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.1 PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 45 Process consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/49 AIS326DQ List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise noted. 10 Electrical characteristics @ Vdd=3.3 V, T = -40 C to 105 C unless otherwise noted . . . 12 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OFFSET_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GAIN_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STATUS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTX_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTX_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTX_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTX_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OUTY_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTZ_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 OUTZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FF_WU_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FF_WU_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FF_WU_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_THS_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_THS_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5/49 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. AIS326DQ FF_WU_THS_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_THS_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FF_WU_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FF_WU_DURATION register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DD_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DD_THSI_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSI_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSI_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSI_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DD_THSE_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6/49 AIS326DQ List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI slave timing diagram (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AIS326DQ electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI Write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 X-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 X-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Y-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Y-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Z-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Z-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 X and Y axes zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 42 X and Y axes sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Z axis sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Recommended land and solder mask design for QFPN packages. . . . . . . . . . . . . . . . . . . 45 QFPN-28 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7/49 Block diagram and pin description AIS326DQ 1 1.1 Block diagram and pin description Block diagram Figure 1. Block diagram X+ Y+ Z+ CHARGE AMPLIFIER MUX DE MUX Reconstruction Filter CS Regs Array SPC SPI SDO/SDI SDO a ZYX- Reconstruction Filter Reconstruction Filter SELF TEST REFERENCE TRIMMING CIRCUITS CLOCK CONTROL LOGIC & INTERRUPT GEN. RDY/INT 1.2 QFPN-28 pin description Figure 2. Pin connection NC NC NC NC NC NC 28 Z 1 Y NC 1 GND Vdd Reserved X GND RDY/INT NC 7 8 Vdd_IO SDO SDI/SDO SPC NC CS 22 21 NC Reserved Vdd Reserved GND CK 15 NC 14 NC AIS326DQ (TOP VIEW) DIRECTIONS OF THE DETECTABLE ACCELERATIONS 8/49 NC AIS326DQ Block diagram and pin description Table 2. Pin# 1 2 3 4 5 6 7, 8 9 10 11 12 13 14, 15 16 17 18 19 20 21 - 28 Pin description Name NC GND Vdd Reserved GND RDY/INT NC SDO SDI/ SDO Vdd_IO SPC CS NC CK GND Reserved Vdd Reserved NC Internally not connected 0 V supply Power supply Either leave unconnected or connect to GND 0 V supply Data ready/inertial wake-up and free-fall interrupt Internally not connected SPI serial data output SPI serial data input (SDI) 3-wire interface serial data output (SDO) Power supply for I/O pads SPI serial port clock Chip select (logic 0: SPI enabled, logic 1: SPI disabled) Internally not connected Optional external clock, if not used either leave unconnected or connect to GND 0 V supply Either leave unconnected or connect to Vdd_IO Power supply Connect to Vdd Internally not connected Function 9/49 Mechanical and electrical specifications AIS326DQ 2 2.1 Table 3. Symbol FS Mechanical and electrical specifications Mechanical characteristics Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise noted(1) Parameter Measurement range(3) Test conditions FS bit set to 0 FS bit set to 1 Full-scale = 2 g T = 25 C, ODR1=40 Hz Full-scale = 2 g T = 25 C, ODR2=160 Hz Dres Device resolution Full-scale = 2 g T = 25 C, ODR3 = 640 Hz Full-scale = 2 g T = 25 C, ODR4 = 2560 Hz Full-scale = 2 g 12 bit representation So Sensitivity Full-scale = 6 g 12 bit representation(4) Full-scale = 2 g 12 bit representation Full-scale = 2 g X, Y axis Full-scale = 2 g Z axis Full-scale = 6 g X, Y axis(4) Full-scale = 6 g Z axis(4) TCOff Zero-g level change vs temperature Max delta from 25 C Best fit straight line X, Y axis Full-scale = 2 g ODR = 40 Hz NL Non linearity(4) Best fit straight line Z axis Full-scale = 2 g ODR = 40 Hz -100 -200 -100 -200 0.2 952 316 Min. 1.7 5.3 Typ.(2) 2.0 g 6.0 1.0 2.0 mg 3.9 15.6 1024 340 0.025 100 200 mg 100 200 mg/C 1096 LSb/g 364 %/C Max. Unit TCSo Sensitivity change vs temperature Off Zero-g level offset accuracy(5),(6) 2 % FS 3 10/49 AIS326DQ Table 3. Symbol CrAx Cross Mechanical and electrical specifications Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise noted(1) (continued) Parameter axis(4) Full-scale= 2 g X axis Full-scale= 2 g Y axis Full-scale= 2 g Z axis Full-scale= 6 g X axis Full-scale= 6 g Y axis Full-scale= 6 g Z axis Test conditions Min. -5 110 110 70 30 30 20 210 210 160 70 70 55 ODRx/4 -40 0.2 +105 Typ.(2) Max. 5 310 310 250 120 120 110 Hz C gram LSb LSb Unit % Vst Self-test output change (7),(8) BW TOP Wh System bandwidth(9) Operating temperature range Product weight 1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended 2. Typical specifications are not guaranteed 3. Verified by wafer level test and specification of initial offset and sensitivity 4. Guaranteed by design 5. Zero-g level offset value after MSL3 preconditioning 6. Offset can be eliminated by enabling the built-in high pass filter (HPF) 7. Self test output changes with the power supply. "Self-test output change" is defined as OUTPUT[LSb](Self-test bit on CTRL_REG1=1) - OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb = 1g/1024 at 12 bit representation, 2 g Full-scale 8. Output data reach 99% of final value after 5/ODR when enabling Self-test mode due to device filtering 9. ODRx is output data rate. Refer to Table 4 for specifications 11/49 Mechanical and electrical specifications AIS326DQ 2.2 Table 4. Symbol Vdd Vdd_IO Idd IddPdn VIH VIL VOH VOL ODR1 ODR2 ODR3 ODR4 BW Ton TOP Electrical characteristics Electrical characteristics @ Vdd=3.3 V, T = -40 C to 105 C unless otherwise noted(1) Parameter Supply voltage I/O pads supply voltage Supply current Current consumption in power-down mode Digital high level Input voltage(3) Digital low level Input voltage High level output voltage(3) Low level output voltage(3) Output data rate 1 Output data rate 2 Output data rate 3 Output data rate 4 System bandwidth Turn-on time (5) (4) (3) (3) Test conditions Min. 3.0 1.71 Typ.(2) 3.3 Max. 3.6 Vdd Unit V V mA A Vdd = 3.3 V 0.67 2 0.8*Vdd_IO 0.80 10 V 0.2*Vdd_IO 0.9*Vdd_IO V 0.1*Vdd_IO Dec factor = 512 Dec factor = 128 Dec factor = 32 Dec factor = 8 40 160 Hz 640 2560 ODRx/4 5/ODRx -40 +105 Hz s C Operating temperature range 1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended 2. Typical specifications are not guaranteed 3. Guaranteed by design 4. Digital filter -3 dB frequency 5. Time to obtain valid data after exiting power-down mode 12/49 AIS326DQ Mechanical and electrical specifications 2.3 2.3.1 Communication interface characteristics SPI - serial peripheral interface Subject to general operating conditions for Vdd and TOP. Table 5. Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 7 50 5 10 5 15 55 ns SPI slave timing values Value(1) Parameter Min 125 8 Max ns MHz Unit 1. Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI slave timing diagram (2) CS (3) (3) tsu(CS) tc(SPC) th(CS) (3) SPC (3) tsu(SI) th(SI) MSB IN LSB IN (3) SDI (3) tv(SO) th(SO) LSB OUT tdis(SO) (3) SDO (3) MSB OUT 2. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both input and output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors 13/49 Mechanical and electrical specifications AIS326DQ 2.4 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol Vdd Vdd_IO Vin Supply voltage(1) I/O pins supply voltage (1) Absolute maximum ratings Ratings Maximum value -0.3 to 6.0 -0.3 to Vdd +0.1 -0.3 to Vdd_IO +0.3 3000 g for 0.5 ms Unit V V V Input voltage on any control pin(1) (CS, SPC, SDI/SDO, SDO, CK) Acceleration (any axis, powered, Vdd = 3.3 V) APOW 10000 g for 0.1 ms 3000 g for 0.5 ms AUNP TOP TSTG Acceleration (any axis, unpowered) Operating temperature range Storage temperature range 10000 g for 0.1 ms -40 to +105 -40 to +125 4.0 (HBM) C C kV V kV ESD Electrostatic discharge protection 200 (MM) 1.5 (CDM) 1. Supply voltage on any pin should never exceed 6.0 V. This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part 14/49 AIS326DQ Mechanical and electrical specifications 2.5 2.5.1 Terminology Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, 1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 Zero-g level Zero-g level offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, 00h with 16 bit representation, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see "Zero-g level change vs. temperature". The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors. 2.5.3 Self test Self test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. The self-test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to `0`. When the self-test bit of CTRL_REG1 is programmed to `1`an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale and depending on the Supply Voltage through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3 or 4 then the sensor is working properly and the parameters of the interface chip are within the defined specification. 15/49 Functionality AIS326DQ 3 Functionality The AIS326DQ is a high performance, low-power, digital output 3-axes linear accelerometer packaged in a QFN package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an SPI serial interface. 3.1 Sensing element A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is up to 100 pF. 3.2 IC interface The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. The converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. The charge amplifier and the converters are operated respectively at 61.5 kHz and 20.5 kHz. The data rate at the output of the reconstruction depends on the user selected decimation factor (DF) and spans from 40 Hz to 2560 Hz. The acceleration data may be accessed through an SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The AIS326DQ features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The AIS326DQ may also be configured to generate an inertial wake-up, direction detection and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. 16/49 AIS326DQ Functionality 3.3 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration. 17/49 Application hints AIS326DQ 4 Application hints Figure 4. AIS326DQ electrical connection 28 22 Z 21 1 Y 1 10uF AIS326DQ (TOP VIEW) X 7 15 100nF 8 14 DIRECTIONS OF THE DETECTABLE ACCELERATIONS Vdd_IO SDO RDY/INT SPC GND Digital signal from/to signal controller. Signal's levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be placed as near as possible to the pin 3 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 4). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the SPI interface. The functions, the thresholds and the timing of the interrupt pin (INT) can be completely programmed by the user through the SPI interface. 18/49 CS Vdd SDI/SDO AIS326DQ Digital interface 5 Digital interface The registers embedded inside the AIS326DQ may be accessed through SPI serial interface. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. Table 7. Serial interface pin description Pin description Chip select (logic 0: SPI enabled, logic 1: SPI disabled) SPI serial port clock SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) Pin name CS SPC SDI/SDO SDO The embedded registers may be accessed also through an I2C interface. For I2C operation refer to LIS3LV02DQ datasheet. 5.1 SPI bus interface The AIS326DQ SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 5. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Read and write protocol SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge 19/49 Digital interface AIS326DQ of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto increased in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is `1' the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. 5.1.1 SPI Read Figure 6. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. 20/49 AIS326DQ Figure 7. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Digital interface Multiple bytes SPI read protocol (2 bytes example) SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 5.1.2 SPI Write Figure 8. SPI Write protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 9. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 Multiple bytes SPI write protocol (2 bytes example) 21/49 Digital interface AIS326DQ 5.1.3 SPI Read in 3-wires mode 3-wires mode is entered by setting to `1' bit SIM (SPI serial interface mode selection) in CTRL_REG2. Figure 10. SPI read protocol in 3-wires mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode. 22/49 AIS326DQ Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address. Table 8. Registers address map Register address Register name Type Binary rw WHO_AM_I r rw OFFSET_X OFFSET_Y OFFSET_Z GAIN_X GAIN_Y GAIN_Z rw rw rw rw rw rw Hex Reserved 00111010 Dummy register Reserved Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Reserved 00000111 00000000 00001000 dummy Dummy register Not used 00000000 output output output output output output Reserved Not used 00000000 00000000 dummy Dummy register Not used 00000000 0000000 - 0001110 00 - 0E 0001111 0F Default Comment 0010000 - 0010101 10 - 15 0010110 0010111 0011000 0011001 0011010 0011011 16 17 18 19 1A 1B 0011100 -0011111 1C-1F CTRL_REG1 CTRL_REG2 CTRL_REG3 rw rw rw 0100000 0100001 0100010 0100011 0100100-0100110 STATUS_REG OUTX_L OUTX_H OUTY_L OUTY_H OUTZ_L OUTZ_H rw r r r r r r r 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 FF_WU_CFG FF_WU_SRC FF_WU_ACK rw rw r 0110000 0110001 0110010 0110011 FF_WU_THS_L rw 0110100 20 21 22 23 24-26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 HP_FILTER RESET r 23/49 Register mapping Table 8. Registers address map (continued) Register address Register name FF_WU_THS_H Type Binary rw 0110101 0110110 0110111 DD_CFG DD_SRC DD_ACK rw rw r 0111000 0111001 0111010 0111011 DD_THSI_L DD_THSI_H DD_THSE_L DD_THSE_H rw rw rw rw 0111100 0111101 0111110 0111111 1000000-1111111 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40-7F 00000000 00000000 00000000 00000000 Reserved 00000000 00000000 dummy Hex 00000000 00000000 Not used Default AIS326DQ Comment FF_WU_DURATION rw Dummy register Not used Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 24/49 AIS326DQ Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 WHO_AM_I (0Fh) Table 9. W7 Register W6 W5 W4 W3 W2 W1 W0 Table 10. W7, W0 Register description AIS326DQ physical address equal to 3Ah Addressing this register the physical address of the device is returned. For AIS326DQ the physical address assigned in factory is 3Ah. 7.2 OFFSET_X (16h) Table 11. OX7 OFFSET_X register OX6 OX5 OX4 OX3 OX2 OX1 OX0 Table 12. OX7, OX0 OFFSET_X register description Digital offset trimming for X-Axis 7.3 OFFSET_Y (17h) Table 13. OY7 OFFSET_Y register OY6 OY5 OY4 OY3 OY2 OY1 OY0 Table 14. OY7, OY0 OFFSET_Y register description Digital offset trimming for Y-Axis 7.4 OFFSET_Z (18h) Table 15. OZ7 OFFSET_Z register OZ6 OZ5 OZ4 OZ3 OZ2 OZ1 OZ0 25/49 Register description AIS326DQ Table 16. OZ7, OZ0 OFFSET_Z register description Digital offset trimming for Z-Axis 7.5 GAIN_X (19h) Table 17. GX7 GAIN_X register GX6 GX5 GX4 GX3 GX2 GX1 GX0 Table 18. GX7, GX0 GAIN_X register description Digital gain trimming for X-Axis 7.6 GAIN_Y (1Ah) Table 19. GY7 GAIN_Y register GY6 GY5 GY4 GY3 GY2 GY1 GY0 Table 20. GY7, GY0 GAIN_Y register description Digital gain trimming for Y-Axis 7.7 GAIN_Z (1Bh) Table 21. GZ7 GAIN_Z register GZ6 GZ5 GZ4 GZ3 GZ2 GZ1 GZ0 Table 22. GZ7, GZ0 GAIN_Z register description Digital gain trimming for Z-Axis 7.8 CTRL_REG1 (20h) Table 23. PD1 CTRL_REG1 register PD0 DF1 DF0 ST Zen Yen Xen Table 24. PD1, PD0 DF1, DF0 CTRL_REG1 register description Power down control (00: power-down mode; 01, 10, 11: device on) Decimation factor control (00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8) 26/49 AIS326DQ Table 24. ST Zen Yen Xen Register description CTRL_REG1 register description (continued) Self test enable (0: normal mode; 1: self-test active) Z-axis enable (0: axis off; 1: axis on) Y-axis enable (0: axis off; 1: axis on) X-axis enable (0: axis off; 1: axis on) PD1, PD0 bit allows to turn the device out of power-down mode. The device is in powerdown mode when PD1, PD0= "00" (default value after boot). The device is in normal mode when either PD1 or PD0 is set to 1. DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The default value is "00" which corresponds to a data-rate of 40 Hz. By changing the content of DF1, DF0 to "01", "10" and "11" the selected data-rate will be set respectively equal to 160 Hz, 640 Hz and to 2560 Hz. ST bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to check the functionality of the whole measurement chain. Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the X-axis measurement channel when set to 1. The default value is 1. 7.9 CTRL_REG2 (21h) Table 25. FS CTRL_REG2 register BDU BLE BOOT IEN DRDY SIM DAS Table 26. FS CTRL_REG2 register description Full scale selection (0: 2 g; 1: 6 g) Block data update (0: continuous update; 1: output registers not updated between MSB and LSB reading) Big/little endian selection (0: little endian; 1: big endian) Reboot memory content Interrupt ENable (0: data ready on RDY pad; 1: interrupt events on RDY pad) Enable data-ready generation BDU BLE BOOT IEN DRDY 27/49 Register description Table 26. SIM DAS AIS326DQ CTRL_REG2 register description (continued) SPI serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) Data alignment selection (0: 12 bit right justified; 1: 16 bit left justified) FS bit is used to select full scale value. After the device power-up the default full scale value is +/-2 g. In order to obtain a +/-6 g full scale it is necessary to set FS bit to `1'. BDU bit is used to inhibit output registers update between the reading of upper and lower register parts. In default mode (BDU = `0') the lower and upper register parts are updated continuously. If it is not sure to read faster than output data rate, it is recommended to set BDU bit to `1'. In this way, after the reading of the lower (upper) register part, the content of that output registers is not updated until the upper (lower) part is read too. This feature avoids reading LSB and MSB related to different samples. BLE bit is used to select Big Endian or Little Endian representation for output registers. In Big Endian's one MSB acceleration value is located at addresses 28h (X-axis), 2Ah (Y-axis) and 2Ch (Z-axis) while LSB acceleration value is located at addresses 29h (X-axis), 2Bh (Yaxis) and 2Dh (Z-axis). In Little Endian representation (Default, BLE=`0`) the order is inverted (refer to data register description for more details). BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. IEN bit is used to switch the value present on data-ready pad between Data-Ready signal and Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to modify DRDY bit to enable Data-Ready signal generation. DRDY bit is used to enable Data-Ready (RDY/INT) pin activation. If DRDY bit is `0' (default value) on Data-Ready pad a `0' value is present. If a Data-Ready signal is desired it is necessary to set to `1' DRDY bit. Data-Ready signal goes to `1' whenever a new data is available for all the enabled axis. For example if Z-axis is disabled, Data-Ready signal goes to `1' when new values are available for both X and Y axis. Data-Ready signal comes back to `0' when all the registers containing values of the enabled axis are read. To be sure not to loose any data coming from the accelerometer data registers must be read before a new Data-Ready rising edge is generated. In this case Data-ready signal will have the same frequency of the data rate chosen. SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA/SDI pad. DAS bit permits to decide between 12 bit right justified and 16 bit left justified representation of data coming from the device. The first case is the default case and the most significant bits are replaced by the bit representing the sign. 28/49 AIS326DQ Register description 7.10 CTRL_REG3 (22h) Table 27. ECK CTRL_REG3 register HPDD HPFF FDS res res CFS1 CFS0 Table 28. ECK HPDD HPFF FDS CTRL_REG3 register description External Clock. Default value: 0 (0: clock from internal oscillator; 1: clock from external pad) High Pass filter enabled for Direction Detection. Default value: 0 (0: filter bypassed; 1: filter enabled) High Pass filter enabled for Free-Fall and Wake-Up. Default value: 0 (0: filter bypassed; 1: filter enabled) Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter) High-pass filter Cut-off Frequency Selection. Default value: 00 (00: Hpc=512 01: Hpc=1024 10: Hpc=2048 11: Hpc=4096) CFS1, CFS0 FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor. CFS1, CFS0 bits defines the coefficient Hpc to be used to calculate the -3dB cut-off frequency of the high pass filter: 0.318 ODRx f cutoff = -------------- ---------------Hpc 2 7.11 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. Read data is not significant. 7.12 STATUS_REG (27h) Table 29. ZYXOR STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA 29/49 Register description AIS326DQ Table 30. ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA STATUS_REG register description X, Y and Z axis data overrun Z axis data overrun Y axis data overrun X axis data overrun X, Y and Z axis new data available Z axis new data available Y axis new data available X axis new data available The content of this register is updated every ODR cycle, regardless of BDU bit value in CTRL_REG2. 7.13 OUTX_L (28h) Table 31. XD7 OUTX_L register XD6 XD5 XD4 XD3 XD2 XD1 XD0 Table 32. XD7, XD0 OUTX_L register description X axis acceleration data LSB In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.14 OUTX_H (29h) Table 33. XD15 OUTX_H register XD14 XD13 XD12 XD11 XD10 XD9 XD8 Table 34. XD15, XD8 OUTX_H register description X axis acceleration data MSB When reading the register in "12 bit right justified" mode the most significant bits (15:12) are replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11). In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the LSB acceleration data. 30/49 AIS326DQ Register description 7.15 OUTY_L (2Ah) Table 35. YD7 OUTY_L register YD6 YD5 YD4 YD3 YD2 YD1 YD0 Table 36. YD7, YD0 OUTY_L register description Y axis acceleration data LSB In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.16 OUTY_H (2Bh) Table 37. YD15 OUTY_H register YD14 YD13 YD12 YD11 YD10 YD9 YD8 Table 38. YD15, YD8 OUTY_H register description Y axis acceleration data MSB When reading the register in "12 bit right justified" mode the most significant bits (15:12) are replaced with bit 11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11). In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the LSB acceleration data. 7.17 OUTZ_L (2Ch) Table 39. ZD7 OUTZ_L register ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 Table 40. ZD7, ZD0 OUTZ_L register description Z axis acceleration data LSB In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 31/49 Register description AIS326DQ 7.18 OUTZ_H (2Dh) Table 41. ZD15 OUTZ_H register ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 Table 42. ZD15, ZD8 OUTZ_H register description Z axis acceleration data MSB When reading the register in "12 bit right justified" mode the most significant bits (15:12) are replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11). In big endian mode (bit BLE in CTRL_REG2 set to `1') the content of this register is the LSB acceleration data. 32/49 AIS326DQ Register description 7.19 FF_WU_CFG (30h) Table 43. AOI FF_WU_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 44. AOI FF_WU_CFG register description And/Or combination of Interrupt events. Default value: 0. (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch interrupt request. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Enable Interrupt request on Z High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable Interrupt request on Z Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable Interrupt request on Y High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable Interrupt request on Y Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable Interrupt request on X High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable Interrupt request on X Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Free-fall and inertial wake-up configuration register. 33/49 Register description AIS326DQ 7.20 FF_WU_SRC (31h) Table 45. X FF_WU_SRC register IA ZH ZL YH YL XH XL Table 46. IA FF_WU_SRC register description Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Z High. Default value: 0 (0: no interrupt; 1: Z High event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y High. Default value: 0 (0: no interrupt; 1: Y High event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: Y Low event has occurred) X High. Default value: 0 (0: no interrupt; 1: X High event has occurred) X Low. Default value: 0 (0: no interrupt; 1: X Low event has occurred) ZH ZL YH YL XH XL 7.21 FF_WU_ACK (32h) Dummy register. If LIR bit in FF_WU_CFG register is set to `1', a reading at this address refreshes the FF_WU_SRC register. Read data is not significant. 7.22 FF_WU_THS_L (34h) Table 47. THS7 FF_WU_THS_L register THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 48. THS7, THS0 FF_WU_THS_L register description Free-fall / inertial wake up acceleration threshold LSB 7.23 FF_WU_THS_H (35h) Table 49. THS15 FF_WU_THS_H register THS14 THS13 THS12 THS11 THS10 THS9 THS8 Table 50. FF_WU_THS_H register description Free-fall / inertial wake up acceleration threshold MSB THS15, THS8 34/49 AIS326DQ Register description 7.24 FF_WU_DURATION (36h) Table 51. FWD7 FF_WU_DURATION register FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0 Table 52. FF_WU_DURATION register description Minimum duration of the Free-fall/Wake-up event FWD7, FWD0 This register sets the minimum duration of the free-fall/wake-up event to be recognized. FF_WU_DURATION (Dec) Duration ( s ) = ----------------------------------------------------------------------ODR 7.25 DD_CFG (38h) Table 53. IEND DD_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 54. IEND DD_CFG register description Interrupt enable on direction change. Default value: 0 (0: disabled; 1: interrupt signal enabled) Latch Interrupt request into DD_SRC reg with the DD_SRC reg cleared by reading DD_ACK reg. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE 35/49 Register description Table 54. XHIE AIS326DQ DD_CFG register description (continued) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) XLIE Direction-detector configuration register. 7.26 DD_SRC (39h) Table 55. X DD_SRC register IA ZH ZL YH YL XH XL Table 56. IA DD_SRC register description Interrupt event from direction change. (0: no direction changes detected; 1: direction has changed from previous measurement) Z High. Default value: 0 (0: Z below THSI threshold; 1: Z accel. exceeding THSE threshold along positive direction of acceleration axis) Z Low. Default value: 0 (0: Z below THSI threshold; 1: Z accel. exceeding THSE threshold along negative direction of acceleration axis) Y High. Default value: 0 (0: Y below THSI threshold; 1: Y accel. exceeding THSE threshold along positive direction of acceleration axis) Y Low. Default value: 0 (0: Y below THSI threshold; 1: Y accel. exceeding THSE threshold along negative direction of acceleration axis) X High. Default value: 0 (0: X below THSI threshold; 1: X accel. exceeding THSE threshold along positive direction of acceleration axis) X Low. Default value: 0 (0: X below THSI threshold; 1: X accel. exceeding THSE threshold along negative direction of acceleration axis) ZH ZL YH YL XH XL Direction detector source register. 36/49 AIS326DQ Register description 7.27 DD_ACK (3Ah) Dummy register. If LIR bit in DD_CFG register is set to `1', a reading at this address refreshes the DD_SRC register. Read data is not significant. 7.28 DD_THSI_L (3Ch) Table 57. THSI7 DD_THSI_L register THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0 Table 58. DD_THSI_L register description Direction detection internal threshold LSB THSI7, THSI0 7.29 DD_THSI_H (3Dh) Table 59. THSI15 DD_THSI_H register THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8 Table 60. DD_THSI_H register description Direction detection internal threshold MSB THSI15, THSI8 7.30 DD_THSE_L (3Eh) Table 61. THSE7 DD_THSE_L register THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0 Table 62. DD_THSE_L register description Direction detection external threshold LSB THSE7, THSE0 7.31 DD_THSE_H (3Fh) Table 63. THSE15 DD_THSE_H register THSE14 THSE13 THSE12 THSE11 THSE10 THSE9 THSE8 Table 64. DD_THSE_H register description Direction detection external threshold MSB THSE15, THSE8 37/49 Typical performance characteristics AIS326DQ 8 8.1 Typical performance characteristics Mechanical characteristics at 25 C Figure 12. X-axis sensitivity at 3.3 V 30 Figure 11. X-axis zero-g level at 3.3 V 45 40 25 35 30 25 20 15 10 5 5 0 -80 0 20 Percent of parts [%] Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 15 10 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Figure 13. Y-axis zero-g level at 3.3 V 40 Figure 14. Y-axis sensitivity at 3.3 V 30 35 25 30 Percent of parts [%] 25 20 Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 20 15 15 10 10 5 5 0 -80 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Figure 15. Z-axis zero-g level at 3.3 V 30 Figure 16. Z-axis sensitivity at 3.3 V 35 25 30 25 Percent of parts [%] Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 20 20 15 15 10 10 5 5 0 -80 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 38/49 AIS326DQ Typical performance characteristics 8.2 Mechanical characteristics at -40 C Figure 18. X-axis sensitivity at 3.3 V 30 Figure 17. X-axis zero-g level at 3.3 V 40 35 25 30 Percent of parts [%] 25 20 Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 20 15 15 10 10 5 5 0 -80 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Figure 19. Y-axis zero-g level at 3.3 V 45 40 Figure 20. Y-axis sensitivity at 3.3 V 30 25 35 30 25 20 15 10 5 5 0 -80 0 20 Percent of parts [%] Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 15 10 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Figure 21. Z-axis zero-g level at 3.3 V 25 Figure 22. Z-axis sensitivity at 3.3 V 30 25 20 Percent of parts [%] 15 Percent of parts [%] -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 20 15 10 10 5 5 0 -80 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 39/49 Typical performance characteristics AIS326DQ 8.3 Mechanical characteristics at 105 C Figure 24. X-axis sensitivity at 3.3 V 30 Figure 23. X-axis zero-g level at 3.3 V 25 25 20 Percent of parts [%] 15 Percent of parts [%] -80 -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 100 20 15 10 10 5 5 0 -100 0 920 940 960 980 1000 1020 Sensitivity [LSB/g] 1040 1060 1080 1100 Figure 25. Y-axis zero-g level at 3.3 V 35 Figure 26. Y-axis sensitivity at 3.3 V 30 30 25 25 Percent of parts [%] 20 Percent of parts [%] -80 -60 -40 -20 0 20 Zero-g Level Offset [mg] 40 60 80 100 20 15 15 10 10 5 5 0 -100 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Figure 27. Z-axis zero-g level at 3.3 V 25 Figure 28. Z-axis sensitivity at 3.3 V 30 25 20 Percent of parts [%] 15 Percent of parts [%] -100 -50 0 50 Zero-g Level Offset [mg] 100 150 20 15 10 10 5 5 0 -150 0 920 940 960 980 1000 1020 Sensitivity [LSB/g] 1040 1060 1080 1100 40/49 AIS326DQ Typical performance characteristics 8.4 Mechanical characteristics derived from measurement in the -40 C to +105 C temperature range Figure 30. X-axis sensitivity change vs. temperature at 3.3 V 5 4 3 2 Figure 29. X-axis zero-g level change vs. temperature at 3.3 V 100 80 60 40 Zero-g Level [mg] 20 0 -20 -40 -60 -80 -100 -50 Sensitivity [%] -25 0 25 50 Temp [oC] 75 100 125 1 0 -1 -2 -3 -4 -5 -50 -25 0 25 50 Temp [oC] 75 100 125 Figure 31. Y-axis zero-g level change vs. temperature at 3.3 V 100 80 60 40 Figure 32. Y-axis sensitivity change vs. temperature at 3.3 V 5 4 3 2 Zero-g Level [mg] 20 0 -20 -40 -60 -80 -100 -50 Sensitivity [%] -25 0 25 50 o Temp [ C] 75 100 125 1 0 -1 -2 -3 -4 -5 -50 -25 0 25 50 o Temp [ C] 75 100 125 Figure 33. Z-axis zero-g level change vs. temperature at 3.3 V 100 80 60 40 Figure 34. Z-axis sensitivity change vs. temperature at 3.3 V 5 4 3 2 Zero-g Level [mg] 20 0 -20 -40 -60 -80 -100 -50 Sensitivity [%] -25 0 25 50 Temp [oC] 75 100 125 1 0 -1 -2 -3 -4 -5 -50 -25 0 25 50 Temp [oC] 75 100 125 41/49 Typical performance characteristics AIS326DQ 8.5 Electro-mechanical characteristics at 25 C Figure 36. X and Y axes sensitivity as function of supply voltage 5 4 3 Figure 35. X and Y axes zero-g level as function of supply voltage 80 60 Normalized Zero-g Level [mg] 40 Normalized Sensitivity [%] 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 2 1 0 -1 -2 -3 20 0 -20 -40 -60 -4 -5 3 -80 3 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 Figure 37. Z axis zero-g level as function of supply voltage 80 60 Figure 38. Z axis sensitivity as function of supply voltage 5 4 3 Normalized Zero-g Level [mg] 40 Normalized Sensitivity [%] 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 2 1 0 -1 -2 -3 20 0 -20 -40 -60 -4 -5 3 -80 3 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 42/49 AIS326DQ Typical performance characteristics 8.6 Electrical characteristics at 25 C Figure 40. Current consumption in operational mode (Vdd=3.3 V) 25 Figure 39. Current consumption in powerdown mode (Vdd=3.3 V) 25 20 20 Percent of parts [%] 15 Percent of parts [%] -1 0 1 2 3 4 Current consumption [uA] 5 6 7 15 10 10 5 5 0 -2 0 500 550 600 650 700 750 Current consumption [uA] 800 850 8.7 Electrical characteristics at -40 C Figure 42. Current consumption in operational mode (Vdd=3.3 V) 25 Figure 41. Current consumption in powerdown mode (Vdd=3.3 V) 30 25 20 Percent of parts [%] Percent of parts [%] -1 0 1 2 3 4 Current consumption [uA] 5 6 7 20 15 15 10 10 5 5 0 -2 0 500 550 600 650 700 750 Current consumption [uA] 800 850 8.8 Electrical characteristics at 105 C Figure 44. Current consumption in operational mode (Vdd=3.3 V) 35 Figure 43. Current consumption in powerdown mode (Vdd=3.3 V) 30 25 30 25 Percent of parts [%] Percent of parts [%] -1 0 1 2 3 4 Current consumption [uA] 5 6 7 20 20 15 15 10 10 5 5 0 -2 0 500 550 600 650 700 750 Current consumption [uA] 800 850 43/49 Soldering information AIS326DQ 9 Soldering information The QFPN-28 package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C, in MSL3 condition. Land pattern and soldering recommendations are also available at www.st.com/. 9.1 General guidelines about soldering surface mount accelerometer As common PCB design and industrial practice when considering accelerometer soldering, there are always 3 elements to take into consideration: 1. 2. PCB with its own conductive layers (i.e. copper) and other organic materials used for board protection and dielectric isolation. ACCELEROMETER to be mounted on the board. Accelerometer senses acceleration, but it senses also the mechanical stress coming from the board. This stress is minimized with simple PCB design rules. SOLDERING PASTE like SnAgCu. This soldering paste can be dispensed on the board with a screen printing method through a stencil. The pattern of the soldering paste on the PCB is given by the stencil mask itself. 3. 9.2 PCB design guidelines PCB land and solder masking general recommendations are shown in Figure 45. Refer to Figure 46 for specific device size, land count and pitch. It is recommended to open solder mask external to PCB land; It is mandatory, for correct device functionality, that some clearance is ensured to be present between accelerometer thermal pad and PCB. In order to obtain this clearance it is recommended to open the PCB thermal pad solder mask; The area below the sensor (on the same side of the board) must be defined as keepout area. It is strongly recommended not to place any structure in top metal layer underneath the sensor; Traces connected to pads should be as much symmetric as possible. Symmetry and balance for pad connection will help component self alignment and will lead to a better control of solder paste reduction after reflow; For better performances over temperature it is strongly recommended not to place large insertion components like buttons or shielding boxes at distance less than 2 mm from the sensor; Central die pad and "Pin 1 Indicator" are physically connected to GND. Leave "Pin 1 Indicator" unconnected during soldering. 44/49 AIS326DQ Soldering information 9.2.1 PCB design rules Figure 45. Recommended land and solder mask design for QFPN packages PACKAGE FOOTPRINT PCB LAND SOLDER MASK OPENING PCB THERMAL PAD NOT TO BE DESIGNED ON PCB PCB THERMAL PAD SOLDER MASK OPENING SUGGESTED TO INCREASE DEVICE THERMAL PAD TO PCB CLEARANCE C A D B A = Clearance from PCB land edge to solder mask opening 0.1 mm to ensure that some solder mask remains between PCB pads B = PCB land length = QFPN solder pad length + 0.1 mm C = PCB land width = QFPN solder pad width + 0.1 mm D = PCB thermal pad solder mask opening = QFPN thermal pad side + 0.2 mm 9.3 Stencil design and solder paste application The thickness and the pattern of the soldering paste are important for the proper accelerometer mounting process. Stainless steel stencils are recommended for solder paste application A stencil thickness of 125 - 150 m (5 - 6 mils) is recommended for screen printing The final thickness of soldering paste should allow proper cleaning of flux residuals and clearance between sensor package and PCB Stencil aperture should have rectangular shape with dimension up to 25 m (1mil) smaller than PCB land The openings of the stencil for the signal pads should be between 50% and 80% of the PCB pad area Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded The fine pitch of the IC leads requires accurate alignment of the stencil to the printed circuit board. The stencil and printed circuit assembly should be aligned to within 25 m (1 mil) prior to application of the solder paste. 45/49 Soldering information AIS326DQ 9.4 Process consideration In case of use of no self-cleaning solder paste it is mandatory proper washing of the board after soldering to eliminate any possible source of leakage between adjacent pads due to flux residues The PCB soldering profile depends on the number, size and placement of components in the application board. It is not functional to define a specific soldering profile for the accelerometer only. Customer should use a time and temperature reflow profile that is derived from the PCB design and manufacturing experience. 46/49 AIS326DQ Package information 10 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK(R) is an ST trademark. ECOPACK(R) specifications are available at: www.st.com. Figure 46. QFPN-28 mechanical data and package dimensions mm DIM. MIN. A A1 A3 b D D1 E E1 e L L1 ddd 0.45 0.30 6.85 4.90 6.85 4.90 0.203 0.35 7.0 5.00 7.0 5.00 0.80 0.55 0.65 0.10 0.08 0.40 7.15 5.10 7.15 5.10 0.012 0.270 0.192 0.270 0.192 0.014 0.275 0.197 0.275 0.197 0.0315 0.018 0..022 0.025 0.004 0.003 1.70 TYP. 1.80 MAX. 1.90 0.05 MIN. 0.067 TYP. 0.071 MAX. 0.075 0.002 0.008 0.016 0.281 0.20 0.281 0.20 inch OUTLINE AND MECHANICAL DATA QFPN-28 (7x7x1.8mm) Quad Flat Package No lead 7787120 C 47/49 Revision history AIS326DQ 11 Revision history Table 65. Date 20-Aug-2008 Document revision history Revision 1 Initial release. Changes 48/49 AIS326DQ Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 49/49 |
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